This invention relates to a labelling circuit for checking a linking state of pixels having logic values of "1" and "0" stored in a two-dimensional image memory in an image processor, and sequentially assigning numbers (labels) to the pixels so as to generate an output image.
Labelling is known as one possible type of image processing, which checks the linking state of the individual pixels of an input image and assigns a specific number (label) to each independent figure. The labelling operation and the configuration of a labelling circuit performing it are disclosed in detail in USP 4,624,013 to the present inventor, entitled "Linked Component Extraction Circuit For Image Processor." FIG. 1 is a block diagram of such a prior art labelling circuit, and FIG. 2 is a block diagram illustrating an image processor provided with the labelling circuit of FIG. 1. In FIG. 2 an image memory 21 stores an input image which is to be subjected to labelling. This input image is transferred in units of pixels to a labelling circuit 10 via an image data bus 31 of an image bus 30.
Labelling circuit 10 has a label extracting circuit (linked component extracting circuit) 11, as shown in FIG. 1. Label extracting circuit 11 receives, through a line 41, the input image that is transferred from image memory 21 via image data bus 31, extracts linked components and then assigns labels to these linked components on the pixel-by-pixel basis. As a result, an intermediate processed image is generated. The intermediate prcessed image is transferred to an image memory 22 via a line 42 and an image data bus 32 for temporary storage.
The intermediate processed image stored in image memory 22 may contain pixel data of identical linked components, but assigned with different labels. In this case, data conversion is required in order to assign the same label to the pixels of the identical linked components. For this purpose, labelling circuit 10 is provided with a table memory 12 which designates when the pixels assigned with different labels are of the identical linked components. To correctly perform the designation, table memory 12 needs proper updating of its contents according to the state of an input image. Label extracting circuit 11 initiates the labelling operation and detects a pixel, which is of the same linked components as another pixel but is assigned with a different label than that of the latter pixel. Upon detection of such an incident, label extracting circuit 11 generates linked information consisting of the labels of those two pixels. One portion of the linked information is supplied to a B input of a selector 13 through a line 43, while the other portion is supplied to a write-data input port W of table memory 12 through a line 44. Consequently, the former portion of the linked information is selected by selector 13 and is supplied, as an address, to an address port A of table memory 12. As a result, the latter portion of the linked information is written into the memory location specified by the address. In this manner, linked information indicating that pixels labelled differently are of the identical linked components is written into table memory 12 in the labelling operation executed by label extracting circuit 11.
Assume now that labelling the entire input image is completed, the entire intermediate processed image is stored in image memory 22, and the contents of table memory 12 are updated in accordance with the input image. In this case, the intermediate processed image is transferred to labelling circuit 10 in units of pixels from image memory 22 and is supplied through a line 45 to an A input of selector 13. Selector 13 in turn selects this intermediate processed image and supplies it to table memory 12 as an address. Consequently, linked information (label value) is read out from the memory location of table memory 12 specified by the address. Accordingly, the intermediate processed image is properly labelled, and becomes a final processed image, which is supplied to a pixel calculation circuit, an image memory or the like (each not shown) through a line 46 and image bus 30.
The contents of table memory 12 of labelling circuit 10 are updated during the labelling operation by label extracting circuit 11. Therefore, it is impossible to perform the labelling operation of a new input image and the data conversion of the previously-generated intermediate processed image in parallel in labelling circuit 10. More specifically, according to the prior art, as shown in FIGS. 3A, 3B, 4A and 4B, a single labelling circuit 10 needs to alternately perform the labelling step (FIGS. 3A and 4A) for labelling an input image to generate an intermediate processed image and the data conversion step (FIGS. 3B and 4B) for subjecting this intermediate processed image to data conversion using table memory 12 to provide an output image (final processed image). This makes it impossible to perform a continuous labelling operation on various input images.